Power LDMOS transistor
Based on Advanced Rugged Technology (ART), this 2000 W LDMOS RF power transistor has been designed to cover a wide range of applications for ISM, broadcast and communications. The unmatched transistor has a frequency range of 1 MHz to 400 MHz.
Features and benefits
- High breakdown voltage enables class E operation up to VDS = 53 V
- Qualified up to a maximum of VDS = 65 V
- Characterized from 30 V to 65 V to support a wide range of applications
- Integrated dual sided ESD protection enables class C operation and complete switch off of the transistor
- Excellent ruggedness with no device degradation
- High efficiency
- Excellent thermal stability
- Designed for broadband operation
- For RoHS compliance see the product details on the Ampleon website
Applications
- Industrial, scientific and medical applications
- Plasma generators
- MRI systems
- CO2 lasers
- Particle accelerators
- Broadcast
- FM radio
- VHF TV
- Communications
- Non cellular communications
- UHF radar
Parametrics
| Symbol | Parameter | Conditions | Min | Typ/Nom | Max | Unit |
|---|---|---|---|---|---|---|
| frange | frequency range | 1 | 400 | MHz | ||
| PL(1dB) | nominal output power at 1 dB gain compression | 2000 | W | |||
| Test signal: Pulsed RF | ||||||
| VDS | drain-source voltage | PL = 2000 W [0] | 65 | V | ||
| Gp | power gain | PL = 2000 W [0] | 27 | 28.4 | dB | |
| RLin | input return loss | PL = 2000 W [0] | -13.9 | dB | ||
| ηD | drain efficiency | PL = 2000 W [0] | 69 | 72.1 | % | |
Package / Packing
| Type number |
Package type, (Package outline) |
Outline version | Packing | Product status | Marking |
Orderable part number, (Ordering code (12NC)) |
|---|---|---|---|---|---|---|
| ART2K0FES | ACC-1230 (SOT539BN) |
sot539bn_po | Tray; 20-fold; non-dry pack | Active | Standard Marking |
ART2K0FESU (9349 605 38112) |
| TR13; 100-fold; 56 mm; non-dry pack | Active | Standard Marking |
ART2K0FESJ (9349 605 38118) |
Pinning info
| Pin | Symbol | Description | Simplified outline | Graphic symbol |
|---|---|---|---|---|
| 1 | D1 | drain1 |
|
|
| 2 | D2 | drain2 | ||
| 3 | G1 | gate1 | ||
| 4 | G2 | gate2 | ||
| 5 | S | source [1] |
Documentation
Recommended line-up
Design support
| Title | Type | Date | |
|---|---|---|---|
| Printed-Circuit Board (PCB) ART2K0FE(S)(G) (Data sheet) | Design support | 2022-03-22 | |
| ART2K0FE(S) Model for ADS 2019 (Keysight Advanced Design System) | Simulation model | 2022-09-28 | |
| ART2K0FE(S) 65 V 100 mA S-parameter data | S-parameter | 2021-02-22 | |
| Model Library for Cadence AWR Microwave Office® | Simulation model | 2023-01-02 | |
| Model Library Manual for Cadence AWR Microwave Office® | Simulation model | 2023-01-02 | |
| Simulation Example for Cadence AWR Microwave Office® | Simulation model | 2023-01-02 | |
| ART2K0FE(S)(G) Foster Thermal Transient Impedance Model | Simulation model | 2023-03-07 | |
| ART2K0FE(S)(G) Cauer Thermal Transient Impedance Model | Simulation model | 2023-03-07 |