LDMOS 2-stage integrated Doherty MMIC

The BLM9D1822S-60PBG is a dual section, 2-stage fully integrated Doherty MMIC solution using Ampleon's state of the art GEN9 LDMOS technology. For each section, the carrier and peaking device, input splitter and output combiner are integrated in a single package. This multiband device is perfectly suited as general purpose driver or small cell final in the frequency range from 1800 MHz to 2200 MHz. Available in gull wing outline.

Features and benefits

  • Integrated input splitter
  • Integrated output combiner
  • High efficiency
  • Designed for broadband operation (frequency 1800 MHz to 2200 MHz)
  • High section-to-section isolation enabling multiple combinations
  • Independent control of carrier and peaking bias
  • Integrated ESD protection
  • Excellent thermal stability
  • Source impedance 50 Ω; high power gain
  • For RoHS compliance see the product details on the Ampleon website

Applications

  • RF power MMIC for multi-carrier and multi-standard GSM, W-CDMA and LTE base stations in the 1800 MHz to 2200 MHz frequency range. Possible circuit topologies are the following:
    • Dual section or single ended
    • Quadrature combined
    • Push-pull

Parametrics

Symbol Parameter Conditions Min Typ/Nom Max Unit
frange frequency range 1800 2200 MHz
PL(3dB) nominal output power at 3 dB gain compression 60 W
Test signal: 1-c LTE 20 MHz
VDS drain-source voltage 1960 MHz [0] 28 V
PL(AV) average output power 1960 MHz [0] 3.16 W
Gp power gain 1960 MHz [0] 28.7 dB
ηD drain efficiency 1960 MHz [0] 22.8 %
ACPR20M adjacent channel power ratio (20 MHz) 1960 MHz [0] -44.1 dBc

Package / Packing

Type number Package Outline version Reflow-/Wave
soldering
Packing Product status Marking Orderable part number,
(Ordering code (12NC))
BLM9D1822S-60PBG OMP-780-16G-1
(OMP-780-16G-1)
omp-780-16g-1_po.pdf Reel 13" Q1/T1 in Drypack Active Standard Marking BLM9D1822S-60PBGY
(9349 602 29518)

Pinning info

Pin Symbol Description Simplified outline Graphic symbol
1 VDS(A1) drain-source voltage of driver stage of section A
2 VGS(A_P) gate-source voltage of peaking of section A
3 VGS(A_C) gate-source voltage of carrier of section A
4 RF_IN_A RF input section A
5 n.c. not connected
6 n.c. not connected
7 n.c. not connected
8 n.c. not connected
9 n.c. not connected
10 n.c. not connected
11 RF_IN_B RF input section B
12 VGS(B_C) gate-source voltage of carrier of section B
13 VGS(B_P) gate-source voltage of peaking of section B
14 VDS(B1) drain-source voltage of driver stages of section B
15 RF_OUT_B/VDS(B2) RF output section B / drain-source voltage of final stages of section B
16 RF_OUT_A/VDS(A2) RF output section A / drain-source voltage of final stages of section A
flange GND RF ground

Quality

Type number Orderable part number Chemical content RoHS / RHF Leadfree conversion date MSL MSL LF
BLM9D1822S-60PBG BLM9D1822S-60PBGY BLM9D1822S-60PBG 3 3
Quality and reliability disclaimer

Design support

Title Type Date
PCB Design BLM9D1822S-60PBG (Data sheet) Design support 2019-04-25